1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit, and particularly to control of gain of the PLL circuit.
2. Description of the Related Art
A PLL circuit effects feedback control to keep a phase difference between an input signal and an output signal of an oscillator constant. A PLL circuit is used for extracting a clock in optical communication or the like. FIG. 16 is a block diagram of a conventional PLL circuit. As shown in FIG. 16, the PLL circuit is formed by a phase comparator 2, a charge pump 4, a low pass filter (LPF) 6, and a voltage-controlled oscillator circuit (VCO) 8. The phase comparator 2 compares the phases of input data such as NRZ data and an output clock of the VCO 8 with each other, and then outputs to the charge pump 4 a phase difference signal indicating a phase difference (indicating the phase difference by a pulse width, for example). The charge pump 4 converts the phase difference signal into a current, and then outputs an output current. The LPF 6 smoothes the output current. The VCO 8 oscillates at an oscillation frequency according to an output voltage of the LPF 6 to output the clock. The output clock of the VCO 8 is inputted to the phase comparator 2 for feedback to the VCO 8, whereby the clock in synchronism with the input data is obtained.
FIG. 17 is a block diagram of FIG. 16. From FIG. 17, a closed loop gain of a feedback loop of the PLL circuit is expressed by an equation (1). An open loop gain of the PLL circuit is expressed by an equation (2).
Open loop gain=Kphxc2x7Ipmpxc2x7F(s)xc2x7Kv/sxe2x80x83xe2x80x83(1) 
Closed loop gain="PHgr"out/"PHgr"in=Kphxc2x7Ipmpxc2x7F(s)xc2x7Kv/{s+Kphxc2x7Ipmpxc2x7F(s)xc2x7Kv}xe2x80x83xe2x80x83(2) 
where Kph is a gain of the phase comparator, for example pulse width/phase difference (s/rad); Ipmp is a current amplitude value (A) of the charge pump; F(s) is a transfer function of the LPF, for example a voltage/current value (xcexa9); and Kv is a gain of the VCO, or frequency/voltage (Hz/V).
FIG. 18 is a diagram showing a complete second-order type loop filter. F(s) of the complete second-order type loop shown in FIG. 18 is expressed by an equation (3).
F(s)=R1(1+1/sC1,R1)xe2x80x83xe2x80x83(3) 
The open loop gain and the closed loop gain when the complete second-order type loop filter is used in the PLL circuit are expressed by equations (4) and (5) by substituting the equation (3) into each of the equations (1) and (2).
Open loop gain=(Kphxc2x7Ipmpxc2x7KvR1/s)xc2x7(1+1/sC1R1)xe2x80x83xe2x80x83(4) 
Closed loop gain={Kphxc2x7Ipmpxc2x7Kvxc2x7(1+sC1R1)}/{s2C1+Kphxc2x7Ipmpxc2x7Kvxc2x7(1+sC1R1)}xe2x80x83xe2x80x83(5) 
FIG. 19 and FIG. 20 are diagrams showing frequency characteristics of the PLL circuit expressed by the equations (4) and (5). In FIG. 19 and FIG. 20, an upper diagram shows a gain characteristic and a phase characteristic of the open loop gain, and a lower diagram shows the closed loop gain. FIG. 19 shows a case where the loop gain is large, and FIG. 20 shows a case where the loop gain is small. The open loop gain is decreased in a range of a low frequency side to 1/R1C1 at 12 dB/oct, and decreased in a range higher than 1/R1C1 at 6 dB/oct. Cut-off frequency of the closed loop gain is a frequency at which the open loop gain is substantially 0 dB, and is in proportion to a loop gain expressed by an equation (6).
Cut-off frequency of the closed loop gain≈loop gain=Kphxc2x7Ipmpxc2x7Kvxc2x7R1xe2x80x83xe2x80x83(6) 
It is to be noted that the equation (6) assumes 1 less than  less than R1C1.
Thus, the cut-off frequency of the closed loop gain is increased in proportion to each of the gains of the phase comparator, the charge pump, and the VCO.
In the case of a large loop gain as shown in FIG. 19, a phase margin is large (90 deg), and the cut-off frequency is high. In the case of a small loop gain as shown in FIG. 20, on the other hand, the phase margin is decreased (about 45 deg), whereby a higher peaking results, and the cut-off frequency is decreased. When the cut-off frequency is increased, high-frequency phase fluctuations are not cut, and thus jitter is increased. When the phase margin is decreased and a higher peaking results, on the other hand, phase fluctuations, or jitter is increased. The closed loop gain characteristic is generally defined by jitter transfer. The closed loop gain of a PLL circuit used for extracting a clock in optical communication and the like is defined by an ITU-T recommendation G958 STM-1 jitter transfer specification.
FIG. 21 is a diagram showing the ITI-T recommendation G958 STM-1 jitter transfer specification. As shown in FIG. 21, this specification specifies that the cut-off frequency be 130 kHz or lower, and the peaking be 0.1 dB or lower. FIG. 22 is a diagram showing PLL frequency characteristics when the loop gain is varied. When the loop gain is too small, the peaking specification cannot be satisfied, as shown in FIG. 22. When the loop gain is too large, on the other hand, the cut-off specification cannot be satisfied, as shown in FIG. 22. Accordingly, in order to satisfy the jitter transfer specification, the loop gain of the PLL circuit needs to be designed to fall between a lower limit value determined by the peaking specification and an upper limit value determined by the cut-off frequency specification.
When a VCO for operating at a high frequency is designed, however, the gain KV of the VCO is varied greatly depending on the process, temperature, and power supply voltage. Therefore, the loop gain is varied greatly, which makes it difficult to satisfy the jitter transfer characteristic. In order to deal with this problem, Japanese Patent Application No. Hei 8-310804 discloses that the loop gain of a PLL circuit is compensated by detecting the VCO gain from a frequency converging characteristic of the PLL circuit. In this example, the VCO gain Kv is detected from a temporal change in VCO control voltage in a converging stage of the PLL circuit. The temporal change in the VCO control voltage is sampled by an A/D converter and calculated by a DSP to thereby detect and compensate the VCO gain. However, in order to detect the temporal change in the VCO control voltage, the PLL circuit needs to be unlocked at some point. It is therefore not possible to respond to a change in the VCO gain due to a variation in the temperature or power supply voltage during continuous operation as of a communication apparatus or the like. In addition, the circuit is complicated because the A/D converter circuit and the DSP are required.
It is accordingly an object of the present invention to provide a PLL circuit that measures the VCO gain during continuous operation with a simple circuit configuration and makes the gain of the PLL circuit constant.
In accordance with an aspect of the present invention, there is provided a PLL circuit having a gain control function, the PLL circuit including: a first phase comparator for outputting a first phase difference signal indicating a phase difference between a first input signal and a second input signal; a first loop filter for smoothing a signal based on the phase difference signal and outputting a first control voltage; a first VCO for oscillating at a frequency based on the first control voltage and thereby outputting a first clock; a dummy VCO having characteristics identical with those of the first VCO for oscillating at a frequency based on a second control voltage and thereby outputting a second clock; a VCO gain detecting circuit for detecting a gain of the first VCO on the basis of a frequency difference between the first clock and the second clock and a voltage difference between the first control voltage and the second control voltage; and a gain control circuit for effecting control so as to make a loop gain constant on the basis of the gain of the first VCO detected by the VCO gain detecting circuit; wherein the second input signal is a signal based on the first clock.
In accordance with another aspect of the present invention, there is provided a PLL circuit having a gain control function, the PLL circuit including: a phase comparator for detecting a phase difference between digital data and a second input signal at a rising edge or a falling edge of the digital data, and outputting a first phase difference signal; a loop filter for smoothing a signal based on the phase difference signal and outputting a control voltage; a VCO for oscillating at a frequency based on the control voltage and thereby outputting a clock; a phase comparator gain detecting circuit for detecting an edge rate, or a rate of rising edges or falling edges of the digital data in a given time; and a gain control circuit for effecting control so as to make a loop gain constant on the basis of the edge rate detected by the phase comparator gain detecting circuit; wherein the second input signal is a signal based on the first clock.
The above and other objects, features and advantages of the present invention and the manner of realizing them will become more apparent, and the invention itself will best be understood from a study of the following description and appended claims with reference to the attached drawings showing some preferred embodiments of the invention.